Method of generating a pulsed output signal from a periodic ramp signal and a reference voltage, and a switch mode power converter

ABSTRACT

In the proposed method of generating a pulsed output signal from a periodic ramp signal and a reference voltage, the linear range of duty cycles of the pulsed output signal is significantly extended to minimum values. The ramp signal and the reference voltage are applied to inputs of a comparator and the output signal is taken from an output of the comparator. The ramp signal has a ramp that extends between a minimum voltage level and a maximum voltage level. The duty cycle of the pulse signal is controlled by varying the reference voltage between the minimum and maximum voltage levels. The ramp has an initial start section extending from the minimum voltage level and a main section extending between the initial section and the maximum voltage level. The ramp slope has a constant value over the main ramp section and a value greater than the constant value over the initial section. In the initial section of the ramp the slope is varied in a manner to compensate for non-linearity of the comparator in an operating range where the reference voltage is close to the minimum voltage level of the ramp signal. It is also preferred to insert a short blanking period before the actual ramp of the waveform. The method can be used in switched mode power converters and in class-d amplifiers.

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 USC § 119 of GermanApplication Serial No. 102004016073.2, filed Mar. 30, 2004.

FIELD OF THE INVENTION

The present invention relates to a method of generating a pulsed outputsignal from a periodic ramp signal and a reference voltage. Such amethod can be used in switch mode power converters and in class-damplifiers. The invention also relates to a switch mode power converterwherein the inventive method is used, and to an oscillator for use in animplementation of the invention.

BACKGROUND OF THE INVENTION

Basically, to generate a pulsed output signal from a periodic rampsignal and a reference voltage, the ramp signal and the referencevoltage are applied to inputs of a comparator. The output signal takenfrom the comparator is the desired pulse signal, the duty cycle of whichis steered by adjusting the reference voltage.

Typical prior art switch mode power converters have a supply input andan output that provides a regulated supply voltage. For example, U.S.Pat. No. 5,600,234 shows a DC-DC buck converter with a switching cellthat transforms an input voltage to a regulated supply voltage lowerthan the input voltage. The switching cell is controlled by a pulsesignal that has a fixed period and a variable duty cycle. The pulsesignal is provided by a summing comparator. The summing comparator has afirst differential input pair to which a saw-tooth waveform signal isapplied that determines the fixed period of the pulse signal. The dutycycle of the pulse signal is set by a first feedback loop that feeds thea fraction of the voltage at the output of the switching cell to aninverting input of the summing comparator, and by a second feedback loopthat includes an integrating differential amplifier. While the firstfeedback loop ensures a fast transient response, it also introduces a DCerror. The second feedback loop has a high gain but slow transientresponse to correct for the DC error and provide a stable steady-stateoperating point.

When switched mode converters and class-d amplifiers operate towardsminimum duty cycles using a periodic signal with a linear saw-toothwaveform, non-linearity present in the comparator has the effect ofincreasing the small-signal gain in the control loop. This destabilizesthe control loop, resulting in a potential for oscillation. Therefore,small minimum values of duty cycle cannot be achieved with conventionalconverters.

SUMMARY OF THE INVENTION

The present invention provides a method of generating a pulsed outputsignal from a periodic ramp signal and a reference voltage, wherein thelinear range of duty cycles of the pulsed output signal is significantlyextended to minimum values. Specifically, the invention provides amethod of generating a pulsed output signal from a periodic ramp signaland a reference voltage, the ramp signal and the reference voltage beingapplied to inputs of a comparator and the output signal being taken froman output of the comparator. The ramp signal has a ramp that extendsbetween a minimum voltage level and a maximum voltage level. The dutycycle of the pulse signal is controlled by varying the reference voltagebetween the minimum and maximum voltage levels. The ramp has an initialstart section extending from the minimum voltage level and a mainsection extending between the initial section and the maximum voltagelevel. The ramp slope has a constant value over the main ramp sectionand a value greater than the constant value over the initial section.

Preferably, the slope in the initial section of the ramp is varied in amanner to compensate for non-linearity of the comparator in an operatingrange where the reference voltage is close to the minimum voltage levelof the ramp signal. It is also preferred to insert a short blankingperiod before the actual ramp of the waveform.

In another aspect of the invention, a switch mode power converter isprovided wherein the principles of the invention are used. The convertercomprises a switching cell with a supply input, an output and a controlinput. A summing comparator has first and second differential inputpairs and an output. The output is connected to the control input of theswitching cell. An oscillator provides a periodic waveform that isapplied to a first one of the inputs of the first differential inputpair of the summing comparator. An adjustable reference voltage sourceprovides an adjustable reference voltage a predetermined fraction ofwhich is applied to a second one of the inputs of the first differentialinput pair of the summing comparator. An error amplifier hasdifferential outputs coupled to the second pair of differential inputsof the summing comparator and a differential input pair. A first inputof the differential input pair is coupled to the output of the switchingcell, and the adjustable reference voltage from the adjustable referencevoltage source is applied to a second input of the differential inputpair. Thus, the desired DC voltage is scaled to produce a DC referencefor the comparator which generates the desired duty cycle for the pulsesignal that drives the switching cell, and thus the desired regulatedoutput voltage, with only minor corrections required across the errorterminals to correct small parasitic terms. To extend the linear rangeof duty cycles of the pulse signal, and thus to extend the linear rangeof available DC output voltage towards small values, the periodicwaveform is a ramp signal having a ramp that extends between a minimumvoltage level and a maximum voltage level, and the ramp of the rampsignal has an initial start section extending from the minimum voltagelevel and a main section extending between the initial section and themaximum voltage level. The slope of the ramp has a constant value overthe main ramp section and a value greater than the constant value overthe initial section. The slope in the initial section of the ramp ispreferably varied in a manner to compensate for non-linearity of thecomparator in an operating range where the reference voltage is close tothe minimum voltage level of the ramp signal.

In a preferred embodiment, a fixed fraction of a demanded output voltagedeveloped at the output of the switching cell is applied to the firstdifferential input of the error amplifier. Thus, the power trainoperates at a fixed gain, and is thus optimally compensated for alloutput voltages.

In a further improvement of this concept, the adjustable referencevoltage source comprises a fixed reference source and an adjustable gainamplifier. A fixed reference voltage from the fixed reference voltagesource is applied to an input of the amplifier and an output of theamplifier provides the adjustable reference voltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic circuit diagram of a switch mode power converteraccording to this invention;

FIG. 2 is a diagram illustrating ideal operation of a converter;

FIG. 3 is a chart showing the shape of narrow output pulses with aconventional converter;

FIG. 4 illustrates the geometry of a saw-tooth ramp used in accordancewith the principles of the invention;

FIG. 5 is a chart showing the shape of narrow output pulses with aconverter operating in accordance with the invention; and

FIG. 6 is a schematic diagram of a circuit in an oscillator forgenerating a saw-tooth signal with the geometry illustrated in FIG. 4.

DETAILED DESCRIPTION OF THE DRAWINGS

With reference to FIG. 1, a DC-DC buck converter is shown with aswitching cell 10 that has a supply port for an input voltage Vin and anoutput port for an output voltage Vout. Switching cell 10 has a pair ofpush-pull transistors MN and MP connected between the supply port andground and a gate driver 12 with outputs connected to the gates oftransistors MN and MP and a control input 14. The connecting nodebetween transistors MN and MP is connected to the output port through aninductor 16. A capacitor C and a resistor R are connected in seriesbetween the output port and ground.

A summing comparator 18 has an output connected to the control input 14of switching cell 10 and two pairs of differential inputs. The firstpair of differential inputs (the “inner” inputs in the figure) isconnected to differential outputs of an error amplifier 20. Theinverting input of the second pair is connected to the output of anoscillator 22 that generates a saw-tooth waveform at a fixed frequency.The non-inverting input of the second pair is connected to a tap node ofa resistive divider that includes series-connected resistors R1 and R2.

A fixed fraction of the output voltage Vout is taken from a resistivedivider with resistors R3 and R4 connected in series between the outputport and ground, and is supplied to an inverting input of erroramplifier 20. An adjustable reference voltage Vref is applied to thenon-inverting input of error amplifier 20 and to resistor R1 at itsterminal opposite its connection with resistor R2. The adjustablereference voltage Vref is provided by the output of a differentialamplifier 24 the gain of which is adjusted by a feedback loop comprisingresistors R5 and R6 connected is series between the output of amplifier24 and ground, the connection node between resistors R5, R6 beingconnected to the inverting input of amplifier 24. A fixed voltage from afixed reference voltage source 26 is applied to the non-inverting inputof amplifier 24.

The converter is preferably implemented as an integrated CMOS circuit.While most of the components shown in the figure will be incorporated inthe integrated circuit (except for the LC filter formed by inductor 16and capacitor C), the resistive divider comprising resistors R5 and R6will be external to the integrated circuit.

In operation, the summing comparator 18 compares the ramp voltage fromoscillator 22 with a fixed fraction of the adjustable reference voltageVref. If the fixed fraction of the reference voltage Vref is half theramp height of the saw-tooth signal, the output of summing comparatorprovides a pulse signal with a 50:50 duty cycle. A larger or lowerreference voltage Vref would shift the cross-point of summing comparator18, resulting in a corresponding change of the duty cycle. The pulsesignal from comparator 18 is amplified in gate driver 12 so switchtransistors MN and MP alternatingly on and off, thereby producing outputvoltage Vout as is well known. The outputs from error amplifier 20 alsoact to shift the cross-point in summing comparator 18 to correct anyerror in output voltage Vout. However, the DC accuracy of the inventivepower converter is inherently high, and so only minor corrections arenecessary to correct small parasitic terms. As a result, a regulatedoutput voltage Vout is obtained the level of which may be adjusted withhigh accuracy in a wide range by adjusting the reference voltage Vrefwith external resistors R5 and R6.

In the preferred embodiment, the ramp height of the saw-tooth signalfrom oscillator 22 is proportional to the level of the input voltage Vinat the supply input. As is well known, the gain of a modulator asdisclosed is equal to the Supply Voltage divided by the ramp height.Having a supply voltage of 2.5 thru 6 volts gives a variation in thegain of 7.6 dB over the supply voltage range. From a ‘load regulation’point of view, the worst case situation is low supply voltage. From acontrol-loop stabilization point of view the worst case is high supplyvoltage. Making the ramp height proportional to the supply results in aconstant gain for the modulator. In a specific embodiment, a defaultramp height of Vin/10 is used.

For a perfect comparator and a perfect (linear) saw-tooth, for a periodT, the change dT in pulse width for a change dRef in reference voltageis equal to:dT=T*dRef/Ramp_height,

-   -   as illustrated in FIG. 2.

Due to non-linearity of the comparator, however, the above equation isnot satisfied when the reference voltage is close to the minimum of thesaw-tooth ramp.

The plot in FIG. 3 shows very fine detail as the modulator referencepotential is moved successively through the region of operation givingrise to narrow pulses (small duty-cycles). It is seen that there is anarea of operation where the high impedance point does not reach thepositive rail (6 v), and that during this area, the time-differencebetween crossing the supply midpoint in falling and rising directionsvaries much quicker than when the reference point is moved to a positionwhere the hi-z (high impedance) point is reaching the supply railbetween the rising and falling edge. The plot attempts to illustrate therapid change in ‘pulse width’ as it is made to vary through the criticalregion. It should be clear that changes in pulse-width with respect tothe ‘reference voltage’ are much greater through this region. Thistranslates into the modulator having a much higher ‘small signal’ gainfor small duty cycles. Eventually, a point is reached where the pulsesgrow almost linearly with offset.

In the method of the invention, a modified geometry is used for thesaw-tooth ramp to compensate for non-linearity of the comparator atsmall duty cycles. With reference to FIG. 4, it is seen that the ramp,starting from the minimum voltage of the ramp, has an initial sectionwith a slope that is greater than the slope in the remaining sectionwhere the slope is constant. In that initial ramp section which, in FIG.4, extends substantially from time 1.35 μs to time 1.40 μs, the slopegradually decreases to converge to that in the linear section. As isalso seen in FIG. 4, a short blanking period is inserted after thefalling edge of the waveform and the initial section of the ramp.

The results are illustrated in FIG. 5. The waveform shown thereinillustrates the voltage at the comparator's high impedance node as thereference voltage is moved through an identical pattern to the scenarioin FIG. 3. What is relevant to observe is the growth in the width of thepulses, and how much more linear it is in comparison to FIG. 3. Thisclearly translates into a “small signal” gain of the comparator beingmuch more constant over a wider range of duty cycles.

FIG. 6 shows a circuit arrangement to be used in an oscillator forgenerating a saw-tooth signal as shown in FIG. 4. Ignoring first allother components contained in the arrangement, a current source Icharges up a capacitor C to generate a linear ramp with slope I/C. AnNMOS transistor NM1 is connected through a resistor R to the rampoutput. The gate of transistor MN1 is connected to a pulsed signalsource S. When the gate of transistor NM1 is high, NM1 will turn on anddivert the charging current fro current source I, thus holding off thegrowth of the ramp until NM1 is turned off. The shape and timing of thewaveform applied to the gate of NM1 can thus be used to shape theoverall ramp output. In particular, the shape and timing are selected toinsert a short blanking period after the falling edge of the waveformand the beginning of the ramp. To accelerate the charging of capacitor Cin the initial ramp section, the ramp output is additionally connectedto the source of an NMOS transistor NM2. The gate of NM2 is connected toa diode-connected NMOS transistor MN3, biased up by a current source I1.A voltage source V provides drain bias for NM2. Diode-connected MN3 hasa W/L (width/length) ratio much smaller than NM2, and therefore, whenthe capacitor C is discharged, the source of NM2 will shunt anadditional current into capacitor C to give an accelerated slope at thebeginning of the ramp. As the ramp voltage rises, transistor MN2 willturn off, thus reducing the ramp slope to the standard I/C.

The above circuit arrangement is but an example of how the modified rampgeometry of FIG. 4 can be obtained easily.

1. A method of generating a pulsed output signal from a periodic rampsignal and a reference voltage, the ramp signal and the referencevoltage being applied to inputs of a comparator and the output signalbeing taken from an output of the comparator, the ramp signal having aramp that extends between a minimum voltage level and a maximum voltagelevel, wherein the duty cycle of the pulse signal is controlled byvarying the reference voltage between the minimum and maximum voltagelevels, and the ramp has an initial start section extending from theminimum voltage level and a main section extending between the initialsection and the maximum voltage level, the slope having a constant valueover the main ramp section and a value greater than the constant valueover the initial section.
 2. The method according to claim 1, whereinthe slope in the initial section of the ramp is varied in a manner tocompensate for non-linearity of the comparator in an operating rangewhere the reference voltage is close to the minimum voltage level. 3.The method according to claim 2, wherein a blanking period is insertedbefore the initial ramp section.
 4. A switch mode power convertercomprising: a switching cell with a supply input, an output and acontrol input; a summing comparator having first and second differentialinput pairs and an output, the output being connected to the controlinput of the switching cell; an oscillator providing a periodic waveformthat is applied to a first one of the inputs of the first differentialinput pair of the summing comparator; an adjustable reference voltagesource providing an adjustable reference voltage a predeterminedfraction of which is applied to a second one of the inputs of the firstdifferential input pair of the summing comparator; and an erroramplifier having differential outputs coupled to the second pair ofdifferential inputs of the summing comparator and a differential inputpair, a first input of said differential input pair being coupled to theoutput of the switching cell, the adjustable reference voltage from theadjustable reference voltage source being applied to a second input ofsaid differential input pair, wherein the periodic signal is a rampsignal having a ramp that extends between a minimum voltage level and amaximum voltage level, the duty cycle of the pulse signal beingcontrolled by varying the reference voltage between the minimum andmaximum voltage levels, and the ramp has an initial start sectionextending from the minimum voltage level and a main section extendingbetween the initial section and the maximum voltage level, the slopehaving a constant value over the main ramp section and a value greaterthan the constant value over the initial section.
 5. The power converteraccording to claim 4, wherein a fixed fraction of a demanded outputvoltage developed at the output of the switching cell is applied to thefirst differential input of the error amplifier.
 6. The power converteraccording to claim 4, wherein the adjustable reference voltage sourcecomprises a fixed reference source, an adjustable gain amplifier havingan input and an output, a fixed reference voltage from the fixedreference voltage source being applied to said input and said outputproviding the adjustable reference voltage.
 7. The power converteraccording to claim 6, further comprising a resistive voltage dividerconnected to the output of the adjustable gain amplifier and providingsaid predetermined fraction of the adjustable reference voltage.
 8. Thepower converter according to claim 6, wherein the adjustable gainamplifier has a feedback loop with an adjustable resistive voltagedivider.
 9. The power converter according to claim 7 and beingimplemented as an integrated CMOS circuit, the resistive voltage dividerbeing external to the integrated circuit.
 10. An oscillator forgenerating a saw-tooth signal for use in a switch mode power converteror in a class-d amplifier, in particular for use in a power converter asdefined in claim 4, comprising a circuit arrangement with: a currentsource (I) connected in series with a capacitor (C), an interconnectionnode between the current source and the capacitor forming an output ofthe oscillator; a first MOS transistor (MN1) connected to theinterconnection node and having a gate connected to a source (S) of apulsed waveform; a second MOS transistor (MN2) having a source connectedto the interconnection node and a drain connected to a bias voltagesource (V); and a third MOS transistor (NM3) which is diode-connectedand up-biased by a current source (I1), the drain and gate of the thirdMOS transistor (MN3) being connected to the gate of the second MOStransistor (MN2).
 11. The oscillator according to claim 10, wherein thepulsed waveform applied to the gate of the first MOS transistor (MN1)has a shape and timing such that a short blanking period is insertedbetween the falling edge of the saw-tooth waveform and the beginning ofthe ramp.